1 | In a design, timing between the clock and data signal is required to be matched. Clock signal is routed in stripline and data signal is routed in microstrip. Then |
2 | The capacitance of a real parallel plate capacitor, of overlap area A and separation h is |
3 | Which of the following has greatest effect in the increase in capacitance of a via |
4 | As the width of the trace of microstrip is increased, the effective dielectric constant |
5 | Consider the inductance of straight wire. Which of the following has greater effect on the inductance of wire. |
6 | A 0603 SMD resistor mounted in normal condition has |
7 | If the separation between the positive and negative traces of a differential microstrip transmission line is increased, without changing the width of the traces of the dielectric material, its differential impedance |
8 | Which of the following is not an example of differential bus |
9 | Which of the following cases needs transmission line instead of an ordinary PCB trace on most urgent basis |
10 | The dielectric loss |
